Dr. Sundaram is a faculty member in the School of Electrical & Computer Engineering at Georgia Tech, ranked 4th in the nation in engineering programs. He is a globally recognized expert in electronics packaging technology with more than 17 years experience in semiconductor and electronic systems packaging technology. He currently directs and manages one of the largest electronics R&D programs in the world, valued at over $10 Million per year. He also directs the largest Glass Packaging program in the world, with more than 50 active global industry members. He has pioneered major technologies including embedded RF passives in organic substrates, chip-last die embedding and glass interposers. In 2001, he co-founded Jacket Micro Devices, a venture capital funded RF/wireless module technology start-up, acquired by AVX, one of the largest component manufacturers in the world. Dr. Sundaram was one of the first researchers worldwide to explore and demonstrate liquid crystal polymers (LCP) for high performance, high temperature and high frequency packaging. Developed several large industry funded R&D programs in the past ten years with total funding in excess of $25M. Led a team of 60 researchers in 1999-2002 to demonstrate the first Digital-RF-Optical module integrated in a single package. Invented a new concept for high power device packaging with exposed back side of die for thermal dissipation, another technology for low temperature Cu-Cu interconnection for high current carrying devices, and is a serial inventor, having filed over 25 GT invention disclosures, with more than ten US and international patents issued, and several more patents pending. Many of these patents have been licensed in exclusive and non-exclusive modes to leading corporations around the world. Has a very strong publication record, with more than 150 publications, publishing on the average 12 articles every year in high-impact journals, conference proceedings and trade magazines. He volunteers his time in several professional societies, and is currently on the Editorial Advisory Board of Chip Scale Review, a leading 3D packaging trade magazine. Serves on the Advanced Packaging Committee of SEMI, is the Chairman of the IEEE CPMT Technical Committee on High Density Substrates and a member of the Executive Council of IMAPS, the largest global packaging society. Organizes and teaches multiple courses on 3D Systems Packaging and High Density Package Fabrication and Assembly Laboratory courses. Current research includes system on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components, bio-medical device packaging, LED packaging, power modules and power electronics device packaging.