The modern computer industry is consistently striving to improve system performance and drive down size factor via the adoption of next-generation packaging techniques. A highly promising design feature for use in developing these new microelectronics is the adoption of 3D packaging, in which the components inside the computer are stacked vertically so that the number of such components can be increased within a small volume area. One of the major challenges in 3D packaging is the fabrication of finely defined and precisely placed deep vertical holes, known as vias, with diameters as small as a few micrometers through the component ICs, which enables vertical communication between them. This result can currently be achieved using plasma etching technology, a time consuming and expensive process that requires specialized equipment that can cost in the hundreds of thousands of dollars, and specialized work spaces that rival the costs of the equipment itself. In order to fully maximize the promise of 3D packaging on a mass scale, this process needs to be simplified and made more cost effective. Recently, the laboratory team of Dr. C.P. Wong and Ph.D. candidate Liyi Li, of the Georgia Institute of Technology, discovered a chemical process that may make 3D packaging development more productive with lower overall costs.
Using a technique the lab developed based on the fundamental physicochemical behavior of semiconductor materials in a simple chemical bath, the team was able to fabricate the high quality vias needed for component communication. The new electronics processing technique, named metal-assisted chemical etching, or MaCE, not only allowed for production at the necessary level of quality, but was also able to be scaled up to process multiple components in a singular batch. The new MaCE process is approximately 2 to 3 times less expensive than the traditional plasma etching technique and can increase manufacturing output by 1-2 orders of magnitude.
The research results for the MaCE packaging process have been published in IEEE Transactions on Components, Packaging and Manufacturing Technology, and orally presented at the 2015 IEEE Electronic Components and Technology Conference (ECTC) in San Diego, CA. The team is now working with industry partners to make the technology applicable for 3D packaging for high-volume production of next-generation microelectronic systems.
This research is funded by NSF grant #1130876.
L. Li, G. Zhang, and C.P. Wong, “Formation of Through Silicon Vias for Silicon Interposer in Wafer Level by Metal-Assisted Chemical Etching” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. PP, issue 99, July 15, 2015. DOI: 10.1109/TCPMT.2015.2443728
~Christa M. Ernst